Nonvolatile semiconductor storage device

ABSTRACT

A nonvolatile semiconductor storage device includes a plurality of cell transistor pairs including a pair of cell transistors sharing a first node connected to a bit line or a source line, and a dummy gate line laid in parallel with gate lines of the cell transistors, the dummy gate line applying an off voltage to a dummy transistor between the cell transistor pairs. The gate lines and the dummy gate line may be laid at equal intervals. A plurality of impurity diffusion layers corresponding to the first node and second nodes of the cell transistors may be formed at equal intervals in a continuous active region.

CROSS REFERENCE TO RELATED APPLICATIONS

This U.S. Application claims priority benefit of Japanese PatentApplication No. 2017-212061 filed in the Japan Patent Office on Nov. 1,2017. Each of the above-referenced applications is hereby incorporatedherein by reference in its entirety.

BACKGROUND

The technology disclosed in the present specification relates to anonvolatile semiconductor storage device.

In the past, a read-only nonvolatile semiconductor storage device(so-called masked read only memory (ROM)) in which desired data or adesired program is written in a manufacturing process thereof has beenused in various applications. Incidentally, Japanese Patent Laid-OpenNo. 2004-303898 can be cited as an example of a related art related tothe above.

SUMMARY

However, there is room for further improvement with regard to variationsin the characteristics of cell transistors in the existing nonvolatilesemiconductor storage device.

In view of the above-described problem discovered by the inventors ofthe present application, according the technology disclosed in thepresent specification, it is desirable to provide a nonvolatilesemiconductor storage device in which cell transistors have smallcharacteristic variations.

A nonvolatile semiconductor storage device disclosed in the presentspecification has a configuration (first configuration) including aplurality of cell transistor pairs including a pair of cell transistorssharing a first node connected to a bit line or a source line, and adummy gate line laid in parallel with gate lines of the celltransistors, the dummy gate line applying an off voltage to a dummytransistor between the cell transistor pairs.

Incidentally, the nonvolatile semiconductor storage device constitutedof the foregoing first configuration preferably has a configuration(second configuration) in which the gate lines and the dummy gate lineare laid at equal intervals.

In addition, the nonvolatile semiconductor storage device constituted ofthe foregoing first or second configuration preferably has aconfiguration (third configuration) in which a plurality of impuritydiffusion layers corresponding to the first node and second nodes of thecell transistors are formed at equal intervals in a continuous activeregion.

In addition, the nonvolatile semiconductor storage device constituted ofthe foregoing third configuration preferably has a configuration (fourthconfiguration) in which a plurality of cell transistors connected to thecommon bit line are formed in one linear active region without a break.

In addition, the nonvolatile semiconductor storage device constituted ofone of the foregoing first to fourth configurations preferably has aconfiguration (fifth configuration) in which data is written to the celltransistors by a contact type of mask programming.

In addition, the nonvolatile semiconductor storage device constituted ofthe foregoing fifth configuration preferably has a configuration (sixthconfiguration) in which presence or absence of connection of secondnodes of the cell transistors to the source line or the bit line is setaccording to the data.

In addition, the nonvolatile semiconductor storage device constituted ofthe foregoing sixth configuration preferably has a configuration(seventh configuration) in which the presence or absence of connectionof the second nodes of the cell transistors to the source line or thebit line is set by presence or absence of a contact, presence or absenceof a via or a through hole, or presence or absence of a metal accordingto the data.

In addition, the nonvolatile semiconductor storage device constituted ofone of the foregoing first to seventh configurations preferably has aconfiguration (eighth configuration) in which the cell transistors are anegative-channel (N-channel) metal oxide semiconductor (MOS)field-effect transistor.

In addition, the nonvolatile semiconductor storage device constituted ofone of the foregoing first to eighth configurations preferably has aconfiguration (ninth configuration) further including an X-decoderconfigured to drive the gate lines, a Y-decoder configured to drive thebit line, a sense amplifier configured to read data via the bit line,and a controller configured to control each part of the device.

In addition, an electronic apparatus disclosed in the presentspecification has a configuration (tenth configuration) including thenonvolatile semiconductor storage device constituted of one of theforegoing first to ninth configurations.

According to the technology disclosed in the present specification, itis possible to provide a nonvolatile semiconductor storage device inwhich cell transistors have small characteristic variations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram depicting a general configuration of anonvolatile semiconductor storage device;

FIG. 2 is a plan view depicting a comparative example of a memory array;

FIG. 3 is a vertical sectional view depicting the comparative example ofthe memory array;

FIG. 4 is an equivalent circuit diagram depicting the comparativeexample of the memory array;

FIG. 5 is a vertical sectional view of assistance in explaining acontact type of mask programming;

FIG. 6 is a plan view depicting an embodiment of a memory array;

FIG. 7 is a vertical sectional view depicting the embodiment of thememory array;

FIG. 8 is an equivalent circuit diagram depicting the embodiment of thememory array;

FIG. 9 is a diagram of characteristic comparison between the comparativeexample and the embodiment;

FIG. 10 is an equivalent circuit diagram depicting a modification of thememory array; and

FIG. 11 is an external view of a smart phone.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS <NonvolatileSemiconductor Storage Device>

FIG. 1 is a block diagram depicting a general configuration of anonvolatile semiconductor storage device. The nonvolatile semiconductorstorage device in the present configuration example includes a memoryarray 10, an X-decoder 20, a Y-decoder 30, a sense amplifier 40, and acontroller 50.

The memory array 10 includes: m gate lines G1 to Gm (=word lines) laidin an X-axis direction; n bit lines BL1 to BLn laid in a Y-axisdirection; and a plurality (=m×n) of memory cells CELL arranged in theform of a matrix along the gate lines G1 to Gm and the bit lines BL1 toBLn. The configuration and operation of the memory array 10 will bedescribed later in detail.

The X-decoder (row decoder) 20 drives the gate lines G1 to Gm accordingto an instruction from the controller 50.

The Y-decoder (column decoder) 30 drives the bit lines BL1 to BLnaccording to an instruction from the controller 50.

The sense amplifier 40 reads data stored in the memory array 10 via thebit lines BL1 to BLn, and outputs the data to the controller 50.

The controller 50 outputs the requested data to the outside of thedevice by controlling parts (the X-decoder 20, the Y-decoder 30, and thesense amplifier 40, or the like) of the device according to a readcommand input from the outside of the device.

<Memory Array (Comparative Example)>

In the following, prior to description of an embodiment of the memoryarray 10, brief description will be made of a comparative example forcomparison with the embodiment. FIGS. 2 to 4 are respectively a planview, a vertical sectional view (=sectional view taken along a lineα1-α2 in FIG. 2), and an equivalent circuit diagram depicting thecomparative example of a memory array 10.

The memory array 10 according to the comparative example is a NOR typemasked ROM in which m cell transistors T*1 to T*m (FIGS. 2 to 4 depictonly cell transistors T11 to T14 or cell transistors T21 to T24) areconnected in parallel with each other for each of n bit lines BL* (where*=1, 2, . . . , n). Incidentally, the cell transistors T11 to T14 andthe cell transistors T21 to T24 are each an N-channel MOS field-effecttransistor, and each correspond to a memory cell CELL in FIG. 1.

Connection relation between the cell transistors T11 to T14 will bedescribed with reference to FIG. 4. Respective gates of the celltransistors T11 to T14 are connected to gate lines G1 to G4. Inaddition, respective drains D (corresponding to a first node) of thecell transistors T11 to T14 are each connected to a bit line BL*. On theother hand, the presence or absence of connection of the sources S(corresponding to a second node) of the respective cell transistors T11to T14 to a source line SL (=GND line) is set by a contact type of maskprogramming according to data to be written to the respective celltransistors T11 to T14.

FIG. 5 is a vertical sectional view of assistance in explaining thecontact type of mask programming. When data “0” is to be written to thecell transistor T11, for example, it suffices to effect conductionbetween an impurity diffusion region N11 corresponding to the source Sof the cell transistor T11 and a metal MTL2 corresponding to the sourceline SL by a contact CONT, a via VIA (or a through hole), and a metalMTL1.

Conversely, when data “1” is to be written to the cell transistor T11,it suffices to effect isolation between the source S of the celltransistor T11 and the source line SL by not forming at least one of thecontact CONT, the via VIA (or a through hole), and the metal MTL1 orMTL2 described above.

Incidentally, in the present figure, an example is cited in which themetal MTL2 in a second layer from the bottom is the source line SL.However, the number of metal layers is arbitrary, and use of a metal inother than the second layer (a first layer, a third layer, a fourthlayer, . . . from the bottom) as the source line SL is also arbitrary.Irrespective of which layer is used as the source line SL, differentdata “0”/“1” can be generated according to whether the impuritydiffusion layer N11 is connected to the source line SL.

In addition, when the data is to be read from the cell transistor T11,it suffices to precharge the bit line BL*, then set the gate line G1 toa high level, and read the signal level (for example a voltage level) ofthe bit line BL* by the sense amplifier 40.

When there is conduction between the source S of the cell transistor T11and the source line SL, for example, turning on the cell transistor T11causes a charge to pass from the bit line BL* to the source line SL. Asa result, the voltage level of the bit line BL* becomes lower than athreshold value, and thus an output signal of the sense amplifier 40 isat a low level (corresponding to data “0”).

When there is isolation between the source S of the cell transistor T11and the source line SL, on the other hand, the charge does not pass fromthe bit line BL* to the source line SL even when the cell transistor T11is turned on. As a result, the voltage level of the bit line BL* becomeshigher than the threshold value, and thus the output signal of the senseamplifier 40 is at a high level (corresponding to data “1”).

The nonvolatile semiconductor storage device 1 thus adopts the contacttype of mask programming (system of setting the presence or absence ofconnection between the source S of the cell transistor and the sourceline SL by the presence or absence of the contact CONT, the presence orabsence of the via VIA (or a through hole), or the presence or absenceof the metal MTL according to data) as a method of writing data to thecell transistor.

The memory array 10 according to the comparative example has a structurewhere the gate lines G1 to G4 are not laid at equal intervals. Thememory array 10 according to the comparative example therefore has aproblem in that the characteristics of the cell transistors T11 to T14(or the cell transistors T21 to T24) tend to vary. This will bedescribed in the following.

As depicted in FIG. 2 and FIG. 3, active regions A11 and A12 (or activeregions A21 and A22) separated from each other by an element isolationlayer ISO (for example shallow trench isolation (STI) or local oxidationof silicon (LOCOS)) are formed in a P-type semiconductor substrate Psubso as to be arranged in one row.

N-type impurity diffusion layers N11 to N13 and N14 to N16 are formed atequal intervals in the active regions A11 and A12, respectively. Inaddition, N-type impurity diffusion layers N21 to N23 and N24 to N26 areformed at equal intervals in the active regions A21 and A22,respectively.

The gate line G1 is linearly laid between the impurity diffusion layersN11 and N12 and between the impurity diffusion layers N21 and N22 so asto intersect each of the active regions A11 and A21. Similarly, the gateline G2 is linearly laid between the impurity diffusion layers N12 andN13 and between the impurity diffusion layers N22 and N23 so as tointersect each of the active regions A11 and A21.

In addition, the gate line G3 is linearly laid between the impuritydiffusion layers N14 and N15 and between the impurity diffusion layersN24 and N25 so as to intersect each of the active regions A12 and A22.Similarly, the gate line G4 is linearly laid between the impuritydiffusion layers N15 and N16 and between the impurity diffusion layersN25 and N26 so as to intersect each of the active regions A12 and A22.

Incidentally, in the memory array 10 having the above-describedstructure, the impurity diffusion layer N11 corresponds to the source Sof the cell transistor T11, and the impurity diffusion layer N13corresponds to the source S of the cell transistor N12. In addition, theimpurity diffusion layer N12 corresponds to the drain D of both of thecell transistors T11 and T12. That is, a cell transistor pair includinga pair of the cell transistors T11 and T12 sharing the drain D with eachother is formed in the active region A11.

Similarly, the impurity diffusion layer N14 corresponds to the source Sof the cell transistor T13, and the impurity diffusion layer N16corresponds to the source S of the cell transistor T14. In addition, theimpurity diffusion layer N15 corresponds to the drain D of both of thecell transistors T13 and T14. That is, a cell transistor pair includinga pair of the cell transistors T13 and T14 sharing the drain D with eachother is formed in the active region A12.

The above is also true for the active regions A21 and A22. Celltransistor pairs (the cell transistors T21 and T22 and the celltransistors T23 and T24) are formed in the active regions A21 and A22,respectively.

Here, as also described earlier, the active region A11 and the activeregion A12 (and the active region A21 and the active region A22) areseparated from each other by the element isolation layer ISO. Therefore,a gate interval d1 between the gate lines G1 and G2 (or the gate linesG3 and G4) between which the element isolation layer ISO is notinterposed and a gate interval d2 between the gate lines G2 and G3between which the element isolation layer ISO is interposed do notnecessarily coincide with each other.

In the memory array 10 according to the comparative example in which thegate lines G1 to G4 are thus not laid at equal intervals, thecharacteristics of the cell transistors T11 to T14 (or the celltransistors T21 to T24) tend to vary. In the following, detaileddescription will be made of a novel structure that can solve thisproblem.

<Memory Array (Embodiment)>

Detailed description will next be made of an embodiment of a memoryarray 10 that can solve the above-described problem. FIGS. 6 to 8 arerespectively a plan view, a vertical sectional view (=sectional viewtaken along a line α1-α2 in FIG. 6), and an equivalent circuit diagramdepicting an embodiment of a memory array 10. Incidentally, the memoryarray 10 according to the present embodiment is characterized in thatelement isolation for cell transistors is performed by using a dummygate DG without using the element isolation layer ISO while the memoryarray 10 according to the present embodiment is based on theaforementioned comparative example (FIGS. 2 to 4). Accordingly,constituent elements similar to those of the comparative example areidentified by the same reference symbols as in FIGS. 2 to 4, and therebyrepeated description thereof will be omitted. In the following,description will be focused on characteristic parts of the presentembodiment.

As a first change, the impurity diffusion layers N11 to N16corresponding to the sources S or the drains D of the respective celltransistors T11 to T14 are formed at equal intervals in one continuousactive region A1 without being separated by the element isolation layerISO. In other words, the cell transistors T11 to T14 are formed in onelinear active region A1 without a break.

Similarly, the impurity diffusion layers N21 to N26 corresponding to thesources S or the drains D of the respective cell transistors T21 to T24are formed at equal intervals in one continuous active region A2 withoutbeing separated by the element isolation layer ISO. That is, the celltransistors T21 to T24 can be said to be formed in one linear activeregion A2 without a break.

In addition, as a second change, instead of providing the elementisolation layer ISO, a dummy gate line DG is laid between the gate lineG2 and the gate line G3. Specifically, the dummy gate line DG is laidbetween the impurity diffusion layers N13 and N14 and between theimpurity diffusion layers N23 and N24 and in parallel with the gatelines G1 to G4 so as to intersect each of the active regions A1 and A2.

Incidentally, as also described earlier, the impurity diffusion layersN11 to N16 and N21 to N26 are formed at equal intervals in thecontinuous active regions A1 and A2, respectively. Hence, the gate linesG1 to G4 and the dummy gate line DG laid between those impuritydiffusion layers are also at equal intervals. More specifically,respective gate intervals between G1 and G2, between G2 and DG, betweenDG and G3, and between G3 and G4 can each be designed to be “d1.”

However, because the above-described dummy gate DG is laid, dummytransistors DT11 and DT21 are respectively formed between the impuritydiffusion layers N13 and N14 and between the impurity diffusion layersN23 and N24, the dummy transistors DT11 and DT21 having one impuritydiffusion layer as a source S, and having the other impurity diffusionlayer as a drain D.

That is, the dummy transistor DT11 is formed between the transistor pairT11 and T12 and the transistor pair T13 and T14. In addition, the dummytransistor DT21 is formed between the transistor pair T21 and T22 andthe transistor pair T23 and T24.

When these dummy transistors DT11 and DT21 are erroneously turned on,the cell transistors T12 and T13 and the cell transistors T22 and T23are short-circuited, so that the memory array 10 does not operateproperly.

Accordingly, it suffices to apply an off voltage (=ground voltage GND)for holding the dummy transistors DT11 and DT21 in an off state at alltimes to the dummy gate line DG.

The structure in which element isolation for the cell transistors isperformed by thus using the dummy gate DG without using the elementisolation layer ISO facilitates manufacturing the memory array 10, andis able to suppress variations in the characteristics of the celltransistors with the gate intervals set uniform.

FIG. 9 is a diagram of characteristic comparison between theaforementioned comparative example (FIGS. 2 to 4: a broken line) and theembodiment (FIGS. 6 to 8: a solid line). Incidentally, an axis ofabscissas in the present diagram indicates a normalized amount of delayof cell transistors (an example of a characteristic value as an index ofcharacteristic variations). In addition, an axis of ordinates in thepresent diagram indicates frequency (number of cell transistors) withrespect to the amount of delay.

As depicted in the diagram, the aforementioned embodiment (solid line)having uniform gate intervals can suppress variations in the amount ofdelay of the cell transistors as compared with the aforementionedcomparative example (broken line) in which the gate intervals are notuniform. It is consequently possible to improve the yield and datareading characteristic of the nonvolatile semiconductor storage device1.

<Modification>

In the comparative example and the embodiment described above, a pair ofcell transistors forming a transistor pair shares a drain D, and thepresence or absence of connection of the sources S of the celltransistors to the source line SL is set according to data to be writtento the respective cell transistors. However, the relation between thedrain D and the sources S can be mutually interchanged.

FIG. 10 is an equivalent circuit diagram depicting a modification of thememory array 10 (example in which the relation between the drains D andthe sources S in the aforementioned FIG. 8 is interchanged). In thepresent modification, the sources S (corresponding to a first node) ofthe respective cell transistors T11 to T14 are each connected to thesource line SL. On the other hand, the presence or absence of connectionof the drains D (corresponding to a second node) of the respective celltransistors T11 to T14 to the bit line BL* is set according to data tobe written to the respective cell transistors.

Also in such a memory array 10, as described earlier, the structure inwhich element isolation for the cell transistors is performed by usingthe dummy gate DG without using the element isolation layer ISOfacilitates manufacturing the memory array 10, and is able to suppressvariations in the characteristics of the cell transistors with gateintervals set uniform.

<Electronic Apparatus>

FIG. 11 is an external view of a smart phone. A smart phone X is anexample of an electronic apparatus including the nonvolatilesemiconductor storage device 1 described thus far as means for storingsystem firmware of the smart phone X or the like in a nonvolatilemanner.

However, objects in which to include the nonvolatile semiconductorstorage device 1 are not at all limited to this, but the nonvolatilesemiconductor storage device 1 can be suitably included also in otherelectronic apparatuses.

<Other Modifications>

It is to be noted that in addition to the foregoing embodiments, varioustechnical features disclosed in the present specification can bemodified in various manners without departing from the spirit of thetechnological creation thereof. In other words, it is to be consideredthat the foregoing embodiments are illustrative in all respects, and notrestrictive. It is to be understood that the technical scope of thepresent technology is not limited to the foregoing embodiments, butincludes meanings equivalent to claims and all modifications as fallwithin the scope.

The technology disclosed in the present specification can for example besuitably used as a technology for suppressing manufacturing variations(variations in the characteristics of cell transistors) in masked ROMsto be included in various electronic apparatuses.

The present disclosure contains subject matter related to that disclosedin Japanese Priority Patent Application JP 2017-212061 filed in theJapan Patent Office on Nov. 1, 2017, the entire content of which ishereby incorporated by reference.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalent thereof.

What is claimed is:
 1. A nonvolatile semiconductor storage devicecomprising: a plurality of cell transistor pairs including a pair ofcell transistors sharing a first node connected to a bit line or asource line; and a dummy gate line laid in parallel with gate lines ofthe cell transistors, the dummy gate line applying an off voltage to adummy transistor between the cell transistor pairs.
 2. The nonvolatilesemiconductor storage device according to claim 1, wherein the gatelines and the dummy gate line are laid at equal intervals.
 3. Thenonvolatile semiconductor storage device according to claim 1, wherein aplurality of impurity diffusion layers corresponding to the first nodeand second nodes of the cell transistors are formed at equal intervalsin a continuous active region.
 4. The nonvolatile semiconductor storagedevice according to claim 3, wherein a plurality of cell transistorsconnected to the common bit line are formed in one linear active regionwithout a break.
 5. The nonvolatile semiconductor storage deviceaccording to claim 1, wherein data is written to the cell transistors bya contact type of mask programming.
 6. The nonvolatile semiconductorstorage device according to claim 5, wherein presence or absence ofconnection of second nodes of the cell transistors to the source line orthe bit line is set according to the data.
 7. The nonvolatilesemiconductor storage device according to claim 6, wherein the presenceor absence of connection of the second nodes of the cell transistors tothe source line or the bit line is set by presence or absence of acontact, presence or absence of a via or a through hole, or presence orabsence of a metal according to the data.
 8. The nonvolatilesemiconductor storage device according to claim 1, wherein the celltransistors are a negative-channel metal oxide semiconductorfield-effect transistor.
 9. The nonvolatile semiconductor storage deviceaccording to claim 1, further comprising: an X-decoder configured todrive the gate lines; a Y-decoder configured to drive the bit line; asense amplifier configured to read data via the bit line; and acontroller configured to control each part of the device.
 10. Anelectronic apparatus comprising: a nonvolatile semiconductor storagedevice including a plurality of cell transistor pairs including a pairof cell transistors sharing a first node connected to a bit line or asource line, and a dummy gate line laid in parallel with gate lines ofthe cell transistors, the dummy gate line applying an off voltage to adummy transistor between the cell transistor pairs.